VLSI Fabrication process

Introduction:

 An Integrated Circuit (IC) is an electronic network fabricated in a single piece of a semiconductor material. The semiconductor surface is subjected to various processing steps in which impurities and other materials are added with specific geometrical patterns The fabrication steps are sequenced to form three dimensional regions that act as a transistors and interconnects that form the network.  

VLSI Fabrication process sequence:

    1.Silicon manufacture 

    2.Wafer processing 

    3.Lithography 

    4.Oxide growth and removal 

    5.Diffusion and ion implantation 

    6.Annealing 

    7.Silicon deposition 

    8.Metallization 

    9.Testing 

    10.Assembly and packaging 

1.Silicon manufacture 

Pure silicon is melted in a pot (1400º C) and a small seed containing the desired crystal orientation is inserted into molten silicon and slowly(1mm/minute) pulled out.

2.Wafer processing 

The silicon crystal  is manufactured as a cylinder (ingot) with a diameter of 8-12 inches(1”=2.54cm). This cylinder is carefully sawed into thin(0.50-0.75 mm thick) disks called wafers, which are later polished and marked for crystal orientation.

  ⇒

3.Lithography 

Designer: Drawing the “layer” patterns on a layout editor.

Silicon Foundry: Masks generation from the layer patterns in the design data base 

Printing: transfer the mask pattern to the wafer surface Process the wafer to physically pattern each layer of the IC. 

(a).Photo resist application: the surface to be patterned is spin-coated with a light-sensitive organic polymer called photoresist

 (b)Printing (exposure): the mask pattern is developed on the photoresist, with UV light exposure depending on the type of photoresist(negative or positive), the exposed or unexposed parts become resistant to certain types of solvents

 (c)Development: the soluble photo resist is chemically removed The developed photo resist acts as a mask for patterning of underlying layers and then is removed. 

   

            

4.Oxide growth and removal 

Oxide can be grown from silicon through heating in an oxidizing atmosphere

 Gate oxide, device isolation

 Oxidation consumes silicon SiO2is deposited on materials other than silicon through reaction between gaseous silicon compounds and oxidizers Insulation between different layers of metallization

 Once the desired shape is patterned with photoresist, the etching process allows unprotected materials to be removed Wet etching: uses chemicals Dry or plasma etching: uses ionized gases.

5 .Diffusion and ion implantation 

 Diffusion: dopants deposited on silicon move through the lattice by thermal diffusion (high temperature process) 

Wells Ion implantation: highly energized donor or acceptor atoms impinge on the surface and travel below it The patterned SiO2serves as an implantation mask Source and Drain regions.

 

6. Annealing Thermal 

annealing is a high temperature process which: 1)allows doping impurities to diffuse further into the bulk. 2)repairs lattice damage caused by the collisions with doping ions.

7.Silicon deposition 

Films of silicon can be added on the surface of a wafer.

1)Epitaxy: growth of a single-crystal semiconductor film on a crystalline sub state 

2)Polysilicon: polycrystalline film with a granular structure obtained through deposition of silicon on an amorphous material MOSFET gates.

    

                             

8.Metallization:

 Metallization is deposition of metal layers by evaporation interconnections 

9.Testing 

 Test that chip operates

 Design errors

 Manufacturing errors 

 A single dust particle or wafer defect kills a die 

 Yields from 90% to < 10% 

 Depends on die size, maturity of process Test each part before shipping to customer 

10.Assembly and packaging 

 Tape out 

 final layout

 Fabrication 6, 8, 12” wafers 

 Optimized for throughput, not latency (10 weeks!)

 Cut into individual dice

 Packaging

 Bond gold wires from die I/O pads to package

 

References:

[1] "Moore's Law to roll on for another decade" (http://news.cnet.com/2100-1001-984051.html). . Retrieved 2011-11-27. "Moore also affirmed he never said transistor count would double every 18 months, as is commonly said. Initially, he said transistors on a chip would double every year. He then recalibrated it to every two years in 1975. David House, an Intel executive at the time, noted that the changes would cause computer performance to double every 18 months."

 [2] Moore, Gordon E. (1965). "Cramming more components onto integrated circuits" (http://download.intel.com/museum/Moores_Law/ Articles-Press_Releases/Gordon_Moore_1965_Article.pdf) (PDF). Electronics Magazine. p. 4. . Retrieved 2006-11-11. [

3] "Excerpts from A Conversation with Gordon Moore: Moore’s Law" (ftp://download.intel.com/museum/Moores_Law/Video-Transcripts/ Excepts_A_Conversation_with_Gordon_Moore.pdf) (PDF). Intel Corporation. 2005. p. 1. . Retrieved 2006-05-02.

 [4] "1965 – "Moore's Law" Predicts the Future of Integrated Circuits" (http://www.computerhistory.org/semiconductor/timeline/ 1965-Moore.html). Computer History Museum. 2007. . Retrieved 2009-03-19. 

[5] Moore 1965, p. 5 

[6] Disco, Cornelius; van der Meulen, Barend (1998). Getting new technologies together (http://books.google.com/books?id=1khslZ-jbgEC& pg=PA206&lpg=PA206&ots=D38v82mSkm&output=html&sig=ACfU3U2jPixZgKq-PYwVPHDpwO2Zt31puQ). New York: Walter de Gruyter. pp. 206–207. ISBN 3-11-015630-X. OCLC 39391108. . Retrieved 23 August 2008.

 [7] Nathan Myhrvold (7 June 2006). "Moore's Law Corollary: Pixel Power" (http://www.nytimes.com/2006/06/07/technology/circuits/ 07essay.html). New York Times. . Retrieved 2011-11-27.

 [8] Rauch, Jonathan (January 2001). "The New Old Economy: Oil, Computers, and the Reinvention of the Earth" (http://www.theatlantic.com/ issues/2001/01/rauch.htm). The Atlantic Monthly. . Retrieved 28 November 2008. 

[9] Keyes, Robert W. (September 2006). "The Impact of Moore's Law" (http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4785857). Solid State Circuits Newsletter. . Retrieved 28 November 2008.

[10]en.wikipedia.org/wiki/VLSI_Technology www.ieee.org www.epfl.ch Principles of CMOS VLSI Design Neil H.E.Weste Kamran Eshraghian