VLSI Technology

Introduction

Very Large Scale Integration (VLSI) is the process of creating an integrated circuit (IC) by connecting millions of MOS transistors on a single chip. VLSI began in the 1970s with the widespread adoption of MOS integrated circuit chips, which allowed the development of complex semiconductor and telecommunication technologies. Microprocessors and memory chips VLSI devices. Before the introduction of VLSI technology, most ICs had limited functions that they could perform. The electronic circuit may contain CPU, ROM, RAM and other glue logic.

History

Large-scale connection was made possible by the widespread adoption of MOS transistors, in fact Kahang discovered Mohamed M. Atala and Davon in 1959 at Bell Labs. Atala proposed the concept of the MOS integrated circuit chip in 1960, and later in 1961 Kahang discovered that the manufacturing facility of MOS transistors could be used for integrated circuits. General Microelectronics introduced the first commercial MOS integrated circuit in 1964. In the early 1970s, MOS integrated circuit technology allowed more than 10,000 transistors to be connected on a single chip. This led to VLSI in the 1970s and 1980s, with thousands of participants. MOS transistors (then hundreds of thousands, then millions and now billions) on one chip.

Earlier semiconductor chips had two transistors. Subsequent advances added more transistors and, as a result, more individual functions or systems merged over time. The first integrated circuit consisted of only a few devices, probably ten diodes, transistors, resistors and capacitors, making it possible to build one or more logic gates in a single device. Now rethinking what is known as small-scale integration (SSI), advances in technology have led to devices with hundreds of logic gates called medium-scale integration (MSI). Further improvements led to systems with mass integration (LSI), i.e. at least a thousand logic gates. Current technology has surpassed this mark and today's microprocessors have millions of gates and billions of individual transistors.

At one time, there was an effort to name and calibrate various levels of large-scale integration above VLSI. Terms like ultra-large-scale integration (ULSI) were used. But the huge number of gates and transistors available on common devices has rendered such fine distinctions moot. Terms suggesting greater than VLSI levels of integration are no longer in widespread use.

In 2008, billion-transistor processors became commercially available. This became more commonplace as semiconductor fabrication advanced from the then-current generation of 65 nm processes. Current designs, unlike the earliest devices, use extensive design automation and automated logic synthesis to lay out the transistors, enabling higher levels of complexity in the resulting logic functionality. Certain high-performance logic blocks like the SRAM (static random-access memory) cell, are still designed by hand to ensure the highest efficiency.

Structural design

Structured VLSI design is a modular method developed by Carver Mead and Lin Conway to protect the microchip area by reducing the interconnect fabric area. This is achieved by the repeated arrangement of rectangular macro blocks that can be connected to each other using wiring by abutment. An example is dividing the layout of the joiner into a line of single bit slice cells. In complex designs this structure can be obtained through a hierarchical niche.

Structured VLSI design became popular in the early 1980s, but its popularity declined after the arrival of placements and routing tools, destroying much of the area through routing, which could withstand Moore's Law due to progress. Starting in hardware descriptive language KARL in the mid-1970s, Rainer Houghtonstein used the term "Structured VLSI Design" (actually "Structured LSI Design"), a process for preventing chaotic spaghetti-structured programs from nesting. Eder echoed Dixestra's structured programming approach.

Difficulties

    As microprocessors become more complex due to technology scaling, microprocessor designers have encountered several challenges which force them to think beyond the design plane, and look ahead to post-silicon:

Process Variation - As photolithography approaches the basic laws of optics, it becomes difficult to obtain high accuracy in doping densities and carved wires and variation increases the probability of errors. Designers must now simulate multiple manufacturing processes in corners or use system-level techniques to deal with the effects of change before they can be certified ready for production.

Strict design rules - Due to lithography and etch issues with scaling, design rules for layout have become more stringent. Designers need to keep in mind the growing list of rules when laying custom circuits. Overhead for custom design has now reached the design point, with many design houses opting for electronic design automation (EDA) tools to automate their design process.

Time / Design Closure - Due to the large number of clock frequencies, designers find it very difficult to distribute and maintain a low clock curve between these high frequency frequency clocks across the chip. This has led to a growing interest in multicore and multiprocessor architectures, as the computing power of all cores can be accelerated overall with a low clock frequency frequency.

First-pass success - As the die size decreases (due to scaling), and as the wafer sizes increase (due to lower production costs), the number of die per wafer increases and the complexity of making the appropriate photomech increases rapidly. Increases. Masks designed for modern technology can cost many millions of dollars. This prevents the old repetition philosophy associated with multiple "spin-cycles" of finding defects in non-recurring spent silicon and promoting first-pass silicon advances. Several design principles have been developed to support this new design flow, including Design for Manufacturing (DFM), Design for Testing (DFT) and Design for X .

    

 

VLSI Fabrication process

Introduction:

 An Integrated Circuit (IC) is an electronic network fabricated in a single piece of a semiconductor material. The semiconductor surface is subjected to various processing steps in which impurities and other materials are added with specific geometrical patterns The fabrication steps are sequenced to form three dimensional regions that act as a transistors and interconnects that form the network.  

VLSI Fabrication process sequence:

    1.Silicon manufacture 

    2.Wafer processing 

    3.Lithography 

    4.Oxide growth and removal 

    5.Diffusion and ion implantation 

    6.Annealing 

    7.Silicon deposition 

    8.Metallization 

    9.Testing 

    10.Assembly and packaging 

1.Silicon manufacture 

Pure silicon is melted in a pot (1400º C) and a small seed containing the desired crystal orientation is inserted into molten silicon and slowly(1mm/minute) pulled out.

2.Wafer processing 

The silicon crystal  is manufactured as a cylinder (ingot) with a diameter of 8-12 inches(1”=2.54cm). This cylinder is carefully sawed into thin(0.50-0.75 mm thick) disks called wafers, which are later polished and marked for crystal orientation.

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3.Lithography 

Designer: Drawing the “layer” patterns on a layout editor.

Silicon Foundry: Masks generation from the layer patterns in the design data base 

Printing: transfer the mask pattern to the wafer surface Process the wafer to physically pattern each layer of the IC. 

(a).Photo resist application: the surface to be patterned is spin-coated with a light-sensitive organic polymer called photoresist

 (b)Printing (exposure): the mask pattern is developed on the photoresist, with UV light exposure depending on the type of photoresist(negative or positive), the exposed or unexposed parts become resistant to certain types of solvents

 (c)Development: the soluble photo resist is chemically removed The developed photo resist acts as a mask for patterning of underlying layers and then is removed. 

   

            

4.Oxide growth and removal 

Oxide can be grown from silicon through heating in an oxidizing atmosphere

 Gate oxide, device isolation

 Oxidation consumes silicon SiO2is deposited on materials other than silicon through reaction between gaseous silicon compounds and oxidizers Insulation between different layers of metallization

 Once the desired shape is patterned with photoresist, the etching process allows unprotected materials to be removed Wet etching: uses chemicals Dry or plasma etching: uses ionized gases.

5 .Diffusion and ion implantation 

 Diffusion: dopants deposited on silicon move through the lattice by thermal diffusion (high temperature process) 

Wells Ion implantation: highly energized donor or acceptor atoms impinge on the surface and travel below it The patterned SiO2serves as an implantation mask Source and Drain regions.

 

6. Annealing Thermal 

annealing is a high temperature process which: 1)allows doping impurities to diffuse further into the bulk. 2)repairs lattice damage caused by the collisions with doping ions.

7.Silicon deposition 

Films of silicon can be added on the surface of a wafer.

1)Epitaxy: growth of a single-crystal semiconductor film on a crystalline sub state 

2)Polysilicon: polycrystalline film with a granular structure obtained through deposition of silicon on an amorphous material MOSFET gates.

    

                             

8.Metallization:

 Metallization is deposition of metal layers by evaporation interconnections 

9.Testing 

 Test that chip operates

 Design errors

 Manufacturing errors 

 A single dust particle or wafer defect kills a die 

 Yields from 90% to < 10% 

 Depends on die size, maturity of process Test each part before shipping to customer 

10.Assembly and packaging 

 Tape out 

 final layout

 Fabrication 6, 8, 12” wafers 

 Optimized for throughput, not latency (10 weeks!)

 Cut into individual dice

 Packaging

 Bond gold wires from die I/O pads to package

 

References:

[1] "Moore's Law to roll on for another decade" (http://news.cnet.com/2100-1001-984051.html). . Retrieved 2011-11-27. "Moore also affirmed he never said transistor count would double every 18 months, as is commonly said. Initially, he said transistors on a chip would double every year. He then recalibrated it to every two years in 1975. David House, an Intel executive at the time, noted that the changes would cause computer performance to double every 18 months."

 [2] Moore, Gordon E. (1965). "Cramming more components onto integrated circuits" (http://download.intel.com/museum/Moores_Law/ Articles-Press_Releases/Gordon_Moore_1965_Article.pdf) (PDF). Electronics Magazine. p. 4. . Retrieved 2006-11-11. [

3] "Excerpts from A Conversation with Gordon Moore: Moore’s Law" (ftp://download.intel.com/museum/Moores_Law/Video-Transcripts/ Excepts_A_Conversation_with_Gordon_Moore.pdf) (PDF). Intel Corporation. 2005. p. 1. . Retrieved 2006-05-02.

 [4] "1965 – "Moore's Law" Predicts the Future of Integrated Circuits" (http://www.computerhistory.org/semiconductor/timeline/ 1965-Moore.html). Computer History Museum. 2007. . Retrieved 2009-03-19. 

[5] Moore 1965, p. 5 

[6] Disco, Cornelius; van der Meulen, Barend (1998). Getting new technologies together (http://books.google.com/books?id=1khslZ-jbgEC& pg=PA206&lpg=PA206&ots=D38v82mSkm&output=html&sig=ACfU3U2jPixZgKq-PYwVPHDpwO2Zt31puQ). New York: Walter de Gruyter. pp. 206–207. ISBN 3-11-015630-X. OCLC 39391108. . Retrieved 23 August 2008.

 [7] Nathan Myhrvold (7 June 2006). "Moore's Law Corollary: Pixel Power" (http://www.nytimes.com/2006/06/07/technology/circuits/ 07essay.html). New York Times. . Retrieved 2011-11-27.

 [8] Rauch, Jonathan (January 2001). "The New Old Economy: Oil, Computers, and the Reinvention of the Earth" (http://www.theatlantic.com/ issues/2001/01/rauch.htm). The Atlantic Monthly. . Retrieved 28 November 2008. 

[9] Keyes, Robert W. (September 2006). "The Impact of Moore's Law" (http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4785857). Solid State Circuits Newsletter. . Retrieved 28 November 2008.

[10]en.wikipedia.org/wiki/VLSI_Technology www.ieee.org www.epfl.ch Principles of CMOS VLSI Design Neil H.E.Weste Kamran Eshraghian